A CMOS Image Sensor (or CIS) architecture is shown in FIG. 1 and can contain a pixel array, surrounded by control logic 100 and a column readout circuit formed by a column readout stage 106 and an output stage 107. The column readout circuit can contain a column-wise programmable gain amplifier (or PGA) and a column-wise analog-to-digital converter (or ADC). The output stage 107 can contain a digital multiplexer and output drivers. Data is output over one or multiple serial output channels. The frame rate of an image sensor is an important parameter. Developments for faster frame rates are needed, required for imaging of fast moving and ultra-short events for scientific and industrial applications. Several measures have been taken to further increase frame rate. A first improvement is by a faster column analog-to-digital (AD or A/D) conversion and faster readout circuits. A fundamental limitation to the speed of an image sensor architecture as shown in FIG. 1 is set by the pixel array. The planar pixel array is composed of row control lines and column output busses. Column busses run over the entire height of the pixel array. For large focal plane arrays, the capacitance of such column output bus can be large (several pF). To sample a pixel signal, the column bus needs to be sampled after settling. With a large column capacitance this can take a considerable amount of time and limit the maximum frame rate with which the sensor can be read out. This is discussed, for example, in “Limitations to the frame rate of high speed image sensors,” G. Meynants, et al., Proc. International Image Sensor Workshop, June 2009, Bergen (available on www.imagesensors.org), which is hereby incorporated by reference.
Solutions have been proposed by reducing the capacitance of the output line. One possible solution is the use of in-pixel AD conversion (see, e.g., “CMOS area image sensors with pixel level A/D conversion”, Boyd Fowler, Ph.D. dissertation, Stanford University, October 1995, which is hereby incorporated by reference). CMOS area image sensor is known with pixel-level analog-to-digital conversion. The A/D conversion is performed using a one-bit first-order sigma delta modulator at each pixel. Such in-pixel ADC avoids a long interconnect between the pixel buffer amplifier and the AD converter. However, this requires a considerable amount of extra circuitry to be put in the pixel, which limits the minimum pixel size that can be realized. Also power dissipation may increase due to this massive parallel circuitry that is active at the same moment in time.
In an image sensor as shown in FIG. 1, the row readout time needs to be decreased to increase frame rate. Part of the row readout time contains the sampling of the signals on the column busses when a row of pixels is selected, commonly referred to as Row Overhead Time or ROT. This ROT is limited by the time needed for accurate settling of the pixel column bus. Only after column settling, the signal of each pixel can be further amplified and AD converted in the column. A known method is pipelining of the pixel sampling process, the amplification process and the AD conversion process by multiple intermediate sampling stages. This is for example described in J. Bogaerts, et al., “High Speed 36 Gbps 12Mpixel global pipelined shutter CMOS image sensor with CDS”, Proc. IISW 2011 (available on www.imagesensors.org), which is hereby incorporated by reference. In this case, the frame rate is determined by the slowest of the pixel sampling, amplification and AD conversion processes. This requires additional sample-and-hold stages in the column amplifier structure, which may be difficult to make and area consuming for small column pitches. In addition, in large arrays, the pixel sampling process can be slowed down due to the large capacitive loads of the pixel column bus.
By means of example, FIG. 2A shows a known column ADC architecture for a typical CMOS image sensor and FIG. 2B a timing chart. The pixel contains a selection switch driven by a control signal “sel.” When activated, the row of pixels is selected and the signal of the pixel sense node it put on the column bus. In this example, this is the signal directly from the photodiode (in a “3T pixel” architecture), but this can also be the voltage of an in-pixel sample stage, or the floating diffusion sense node of a classical “4T” active pixel with in-pixel charge transfer. The signal of the column bus is sampled in the column amplifier in a sample-and-hold stage, controlled by a “sample” signal. In principle, a programmable gain amplifier could be present in the column structure before or after this sampling stage but this is not shown in the figure. The signal can be sampled after settling on the column bus. The sampled signal can then be converted into a digital value by the column AD circuit shown. This circuit contains a comparator, a counter and an SRAM buffer. The counter is reset at the start of the AD conversion process. The signal of the sample-and-hold stage is applied to the comparator. A sloped ramp signal is applied at the other input of the comparator. The output of the comparator enables or disables a counter depending on the output of the comparison. After the start of the ramp, the counter is clocked and enabled until the ramp signal crosses the signal stored in the column sample-and-hold stage. At the end of the conversion cycle, the counter contains a digital value representative of the signal of the pixel. The structure shown is simplified. Several variants have been proposed in the past with multiple counters (see, e.g., U.S. Pat. No. 9,041,581 to Wolfs, entitled “Analog-to-Digital Conversion” and issued May 26, 2015, which is hereby incorporated by reference) or with dual ramp conversion cycles to allow correlated double sampling (see, e.g., European Patent Publication No. EP2109223 by Bogaerts, entitled “Analog-to-digital conversion in pixel arrays” and filed Feb. 19, 2009, which is hereby incorporated by reference). Other implementations use a latch instead of a counter. When the comparator toggles, the latch latches a digital value that is distributed to the column structures and that is representative of the moment in time when the comparator toggled. This is for example described in C. Jansson, et al, “An Addressable 256×256 Photodiode Image Sensor Array with an 8-bit Digital Output,” Analog Integrated Circuits and Signal Processing 4, 37-49 (1993), Kluwer, which is hereby incorporated by reference. In all cases, there is a settling time between the selection of the pixel and the moment when the signal present on the column can be sampled, which is determined by the capacitance of the column bus (Cbus), the dimensions of the pixel source follower, and the bias current through this source follower.
A further design is known from Yue Chen, Yang Xu, Youngcheol Chae, Adri Mierop, Xinyang Wang, Albert Theuwissen, “A 0.7 e-rms Temporal Readout Noise CMOS Image Sensor for Low-Light-Level Imaging,” International Solid-State Circuits Conference (ISSCC), San Francisco, Digest Tech. Papers, pp. 384-385, Feb. 19-23, 2012, which is hereby incorporated by reference.